EP2S90F1020C5 Datasheet, PDF (401/768 Pages) Altera Corporation – Stratix II Device Handbook, Volume 1

External Memory Interfaces in Stratix II and Stratix II GX Devices
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to any of Stratix II and Stratix II GX I/O pins in the same bank as the DQ
pins of the FPGA. There is one DM pin per DQS/DQ group in a DDR or
DDR2 SDRAM device.
You can also use I/O pins in banks 1, 2, 5, or 6 to interface with DDR and
DDR2 SDRAM devices. These banks do not have dedicated circuitry,
though, and can only support DDR SDRAM at speeds up to 150 MHz and
DDR2 SDRAM at speeds up to 200 MHz. DDR2 SDRAM interfaces using
these banks are supported using the SSTL-18 Class I I/O standard.
For more information, see AN 327: Interfacing DDR SDRAM with
Stratix II Devices and AN 328: Interfacing DDR2 SDRAM with Stratix II
Devices.
If the DDR or DDR2 SDRAM device supports error correction coding
(ECC), the design will use an extra DQS/DQ group for the ECC pins.
You can use any of the user I/O pins for commands and addresses to the
DDR and DDR2 SDRAM. You may need to generate these signals from
the system clock’s negative edge.
The clocks to the SDRAM device are called CK and CK# pins. Use any of
the user I/O pins via the DDR registers to generate the CK and CK#
signals to meet the DDR SDRAM or DDR2 SDRAM device’s t_DQSS
requirement. The memory device’s t_DQSS specification requires that the
write DQS signal’s positive edge must be within 25% of the positive edge
of the DDR SDRAM or DDR2 SDRAM clock input. Using regular I/O
pins for CK and CK# also ensures that any PVT variations on the DQS
signals are tracked the same way by these CK and CK# pins. Figure 3–2
shows a diagram that illustrates how to generate these clocks.
Altera Corporation
January 2008
3–5
Stratix II Device Handbook, Volume 2