EP2S90F1020C5 Datasheet, PDF (423/768 Pages) Altera Corporation – Stratix II Device Handbook, Volume 1

External Memory Interfaces in Stratix II and Stratix II GX Devices
Figure 3–10. Simplified Diagram of the DQS Phase-Shift Circuitry Note (1)
addnsub
Phase offset settings
DLL
from the logic array
Input reference
clock (2)
upndn
Phase
Comparator clock enable
Up/Down
Counter
6
Phase
Offset
Control 6
Phase offset
settings (3)
6
Delay Chains
DQS delay
6
settings (4)
6
Notes to Figure 3–10:
(1) All features of the DQS phase-shift circuitry are accessible from the altdqs megafunction in the Quartus II software.
You should; however, use Altera’s memory controller IP Tool Bench to generate the data path for your memory
interface.
(2) The input reference clock for the DQS phase-shift circuitry on the top side of the device can come from
CLK[15..12]p or PLL 5. The input reference clock for the DQS phase-shift circuitry on the bottom side of the
device can come from CLK[7..4]p or PLL 6.
(3) Phase offset settings can only go to the DQS logic blocks.
(4) DQS delay settings can go to the logic array and/or to the DQS logic block.
The input reference clock goes into the DLL to a chain of up to 16 delay
elements. The phase comparator compares the signal coming out of the
end of the delay element chain to the input reference clock. The phase
comparator then issues the upndn signal to the up/down counter. This
signal increments or decrements a six-bit delay setting (DQS delay
settings) that will increase or decrease the delay through the delay
element chain to bring the input reference clock and the signals coming
out of the delay element chain in phase.
The DQS delay settings contain the control bits to shift the signal on the
input DQS pin by the amount set in the altdqs megafunction. For the 0°
shift, both the DLL and the DQS logic block are bypassed. Since Stratix II
and Stratix II GX DQS and DQ pins are designed such that the pin to IOE
delays are matched, the skew between the DQ and DQS pin at the DQ IOE
registers is negligible when the 0° shift is implemented. You can feed the
DQS delay settings to the DQS logic block and the logic array.
Altera Corporation
January 2008
3–27
Stratix II Device Handbook, Volume 2