EP2S90F1020C5 Datasheet, PDF (330/768 Pages) Altera Corporation – Stratix II Device Handbook, Volume 1

Clocking
dual-regional clock network. Corner fast PLL outputs only span one
quadrant and hence cannot form a dual-regional clock network.
Figure 1–42 shows this feature pictorially.
Figure 1–42. Stratix II and Stratix II GX Dual-Regional Clock Region
Clock pins or PLL outputs
can drive half of the device to
create dual-reginal clocking
regions for improved I/O
interface timing.
The 16 clock input pins, enhanced or fast PLL outputs, and internal logic
array can be the clock input sources to drive onto either global or regional
clock networks. The CLKn pins also drive the global clock network as
shown in Table 1–22 on page 1–72. Tables 1–18 and 1–19 for the
connectivity between CLK pins as well as the global and regional clock
networks.
Clock Inputs
The clock input pins CLK[15..0] are also used for high fan-out control
signals, such as asynchronous clears, presets, clock enables, or protocol
signals such as TRDY and IRDY for PCI through global or regional clock
networks.
Internal Logic Array
Each global and regional clock network can also be driven by logic-array
routing to enable internal logic to drive a high fan-out, low-skew signal.
PLL Outputs
All clock networks can be driven by the PLL counter outputs.
1–66
Stratix II Device Handbook, Volume 2
Altera Corporation
July 2009