EP2S90F1020C5 Datasheet, PDF (370/768 Pages) Altera Corporation – Stratix II Device Handbook, Volume 1

Memory Modes
1 TriMatrix memory does not support asynchronous memory
(unregistered inputs).
Depending on which TriMatrix memory block you use, the memory has
various modes, including:
■ Single-port
■ Simple dual-port
■ True dual-port (bidirectional dual-port)
■ Shift-register
■ ROM
■ FIFO
1 Violating the setup or hold time on the memory block address
registers could corrupt memory contents. This applies to both
read and write operations.
Single-Port Mode
All TriMatrix memory blocks support the single-port mode that supports
non-simultaneous read and write operations. Figure 2–5 shows the
single-port memory configuration for TriMatrix memory.
Figure 2–5. Single-Port Memory Note (1)
data[ ]
address[ ]
wren
byteena[]
addressstall
inclock
inclocken
q[]
outclock
outclocken
outaclr
Note to Figure 2–5:
(1) Two single-port memory blocks can be implemented in a single M4K or M-RAM
block.
M4K and M-RAM memory blocks can also be halved and used for two
independent single-port RAM blocks. The Altera^® Quartus^® II software
automatically uses this single-port memory packing when running low
on memory resources. To force two single-port memories into one M4K
or M-RAM block, first ensure that each of the two independent RAM
blocks is equal to or less than half the size of the M4K or M-RAM block.
Secondly, assign both single-port RAMs to the same M4K or M-RAM
block.
2–10
Stratix II Device Handbook, Volume 2
Altera Corporation
January 2008