EP2S90F1020C5 Datasheet, PDF (589/768 Pages) Altera Corporation – Stratix II Device Handbook, Volume 1

Altera Corporation
January 2008
Configuring Stratix II and Stratix II GX Devices
1
To begin configuration, power the V_CCINT, V_CCIO, and V_CCPD
voltages (for the banks where the configuration and JTAG pins
reside) to the appropriate voltage levels.
The serial clock (DCLK) generated by the Stratix II and Stratix II GX
devices controls the entire configuration cycle and provides the timing for
the serial interface. Stratix II and Stratix II GX devices use an internal
oscillator to generate DCLK. Using the MSEL[] pins, you can select to use
either a 40- or 20-MHz oscillator.
1 Only the EPCS16 and EPCS64 devices support a DCLK up to
40-MHz clock; other EPCS devices support a DCLK up to
20-MHz. Refer to the Serial Configuration Devices Data Sheet for
more information. The EPCS4 device only supports the smallest
Stratix II (EP2S15) device, which is when the SOF compression
is enabled. Because of its insufficient memory capacity, the
EPCS1 device does not support any Stratix II devices.
Table 7–12 shows the active serial DCLK output frequencies.
Table 7–12. Active Serial DCLK Output Frequency
Oscillator
40 MHz (1)
20 MHz
Minimum
20
10
Typical
26
13
Maximum
40
20
Units
MHz
MHz
Note to Table 7–12:
(1) Only the EPCS16 and EPCS64 devices support a DCLK up to 40-MHz clock; other
EPCS devices support a DCLK up to 20-MHz. Refer to the Serial Configuration
Devices (EPCS1, EPCS4, EPCS16, EPCS16, and EPCS128) Data Sheet chapter in
volume 2 of the Configuration Handbook for more information.
In both AS and fast AS configuration schemes, the serial configuration
device latches input and control signals on the rising edge of DCLK and
drives out configuration data on the falling edge. Stratix II and
Stratix II GX devices drive out control signals on the falling edge of DCLK
and latch configuration data on the falling edge of DCLK.
In configuration mode, Stratix II and Stratix II GX devices enable the
serial configuration device by driving the nCSO output pin low, which
connects to the chip select (nCS) pin of the configuration device. The
Stratix II and Stratix II GX devices use the serial clock (DCLK) and serial
data output (ASDO) pins to send operation commands and/or read
address signals to the serial configuration device. The configuration
device provides data on its serial data output (DATA) pin, which connects
to the DATA0 input of the Stratix II and Stratix II GX devices.
7–37
Stratix II Device Handbook, Volume 2