EP2S90F1020C5 Datasheet, PDF (310/768 Pages) Altera Corporation – Stratix II Device Handbook, Volume 1

Reconfigurable Bandwidth
The bandwidth and stability of such a system is determined by the charge
pump current, the loop filter resistor value, the high-frequency capacitor
value (in the loop filter), and the m-counter value. You can use the
Quartus II software to control these factors and to set the bandwidth to
the desired value within a given range.
You can set the bandwidth to the appropriate value to balance the need
for jitter filtering and lock time. Figures 1–27 and 1–28 show the output of
a low- and high-bandwidth PLL, respectively, as it locks onto the input
clock.
Figure 1–27. Low-Bandwidth PLL Lock Time
160
155
Lock Time = 8 μs
150
145
Frequency (MHz)
140
135
130
125
120
0
5
10
15
Time (μs)
1–46
Stratix II Device Handbook, Volume 2
Altera Corporation
July 2009