EP2S90F1020C5 Datasheet, PDF (605/768 Pages) Altera Corporation – Stratix II Device Handbook, Volume 1

Configuring Stratix II and Stratix II GX Devices
f
For more information on configuring multiple Altera devices in the same
configuration chain, refer to the Configuring Mixed Altera FPGA Chains
chapter in volume 2 of the Configuration Handbook.
PS Configuration Timing
Figure 7–20 shows the timing waveform for PS configuration when using
a MAX II device as an external host.
Figure 7–20. PS Configuration Timing Waveform
nCONFIG
t_CF2ST1
t_CFG
t_CF2CK
Note (1)
nSTATUS (2)
CONF_DONE (3)
DCLK
DATA
User I/O
INIT_DONE
t_STATUS
t_CF2ST0
t_CLK
t_CF2CD
t_CH t_CL
t_ST2CK
t_DH
Bit 0 Bit 1
t_DSU
Bit 2
Bit 3
High-Z
Bit n
(4)
(4)
User Mode
t_CD2UM
Notes to Figure 7–20:
(1) The beginning of this waveform shows the device in user-mode. In user-mode, nCONFIG, nSTATUS and
CONF_DONE are at logic high levels. When nCONFIG is pulled low, a reconfiguration cycle begins.
(2) Upon power-up, the Stratix II or Stratix II GX device holds nSTATUS low for the time of the POR delay.
(3) Upon power-up, before and during configuration, CONF_DONE is low.
(4) DCLK should not be left floating after configuration. It should be driven high or low, whichever is more convenient.
DATA[0] is available as a user I/O pin after configuration and the state of this pin depends on the dual-purpose pin
settings.
Table 7–15 defines the timing parameters for Stratix II and Stratix II GX
devices for PS configuration.
Table 7–15. PS Timing Parameters for Stratix II and Stratix II GX Devices (Part 1 of 2)
Symbol
Parameter
t_CF2CD
t_CF2ST0
nCONFIG low to CONF_DONE low
nCONFIG low to nSTATUS low
Min
Max
800
800
Units
ns
ns
Altera Corporation
January 2008
7–53
Stratix II Device Handbook, Volume 2