EP2S90F1020C5 Datasheet, PDF (378/768 Pages) Altera Corporation – Stratix II Device Handbook, Volume 1

Memory Modes
Figure 2–10 shows true dual-port timing waveforms for the write
operation at port A and the read operation at port B.
Figure 2–10. Stratix II and Stratix II GX True Dual-Port Timing Waveforms
clk_a
wren_a
address_a
data_a (1)
q_a (synch)
q_a (asynch)
clk_b
wren_b
address_b
q_b (synch)
q_b (asynch)
an-1
din-1
an
din
din-2
din-1
a0
din-1
din
bn
doutn-2
doutn-1
b0
doutn-1
doutn
a1
a2
a3
a4
a5
din
dout0
dout0
dout1
dout1
dout2
din4
din5
dout2
dout3
dout3
din4
a6
din6
din4
din5
b1
doutn
dout0
b2
dout0
dout1
b3
dout1
dout2
Note to Figure 2–10:
(1) The crosses in the data_a waveform during write mean “don’t care.”
Shift-Register Mode
All Stratix II memory blocks support the shift register mode.
Embedded memory block configurations can implement shift registers
for digital signal processing (DSP) applications, such as finite impulse
response (FIR) filters, pseudo-random number generators, multi-channel
filtering, and auto-correlation and cross-correlation functions. These and
other DSP applications require local data storage, traditionally
implemented with standard flip-flops that quickly exhaust many logic
cells for large shift registers. A more efficient alternative is to use
embedded memory as a shift-register block, which saves logic cell and
routing resources.
The size of a (w × m × n) shift register is determined by the input data
width (w), the length of the taps (m), and the number of taps (n), and
must be less than or equal to the maximum number of memory bits in the
respective block: 576 bits for the M512 block, 4,608 bits for the M4K block,
and 589,824 bits for the MRAM block. In addition, the size of w × n must
be less than or equal to the maximum width of the respective block: 18
2–18
Stratix II Device Handbook, Volume 2
Altera Corporation
January 2008