EP2S90F1020C5 Datasheet, PDF (496/768 Pages) Altera Corporation – Stratix II Device Handbook, Volume 1

Differential I/O Termination
Synchronizer
The synchronizer is a 1-bit  6-bit deep FIFO buffer that compensates for
the phase difference between the recovered clock from the DPA circuit
and the diffioclk that clocks the rest of the logic in the receiver. The
synchronizer can only compensate for phase differences, not frequency
differences between the data and the receiver’s INCLK. An optional port,
RX_FIFO_RESET, is available to the internal logic to reset the
synchronizer. The synchronizer is automatically reset when the DPA first
locks to the incoming data. Altera^® recommends using RX_FIFO_RESET
to reset the synchronizer when the DPA signals a loss-of-lock condition
beyond the initial locking condition.
Differential I/O
Termination
f
Stratix II and Stratix II GX devices provide an on-chip 100-differential
termination option on each differential receiver channel for LVDS and
HyperTransport standards. The on-chip termination eliminates the need
to supply an external termination resistor, simplifying the board design
and reducing reflections caused by stubs between the buffer and the
termination resistor. You can enable on-chip termination in the Quartus II
assignments editor. Differential on-chip termination is supported across
the full range of supported differential data rates.
For more information, refer to the High-Speed I/O Specifications section
of the DC & Switching Characteristics chapter in volume 1 of the Stratix II
Device Handbook or the High-Speed I/O Specifications section of the
DC & Switching Characteristics chapter in volume 1 of the Stratix II GX
Device Handbook.
Figure 5–11 illustrates on-chip termination.
Figure 5–11. On-Chip Differential Termination
LVDS/HT
Transmitter
Z₀ = 50 Ω
Stratix II Differential
Receiver with On-Chip
100 Ω Termination
R_D
Z₀ = 50 Ω
On-chip differential termination is supported on all row I/O pins and on
clock pins CLK[0, 2, 8, 10]. The clock pins CLK[1, 3, 9, 11],
and FPLL[7..10]CLK, and the clocks in the top and bottom I/O banks
(CLK[4..7, 12..15]) do not support differential on-chip termination.
5–12
Stratix II Device Handbook, Volume 2
Altera Corporation
January 2008