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EP2S90F1020C5 Datasheet, PDF (349/768 Pages) Altera Corporation – Stratix II Device Handbook, Volume 1 | |||
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PLLs in Stratix II and Stratix II GX Devices
Figure 1â50. Stratix II Corner Fast PLLs, Clock Pin and Logic Array Signal
Connectivity to Global and Regional Clock Networks Note (1)
Note to Figure 1â50:
(1) The corner FPLLs can also be driven through the global or regional clock networks.
The global or regional clock input can be driven by an output from another PLL, a
pin-driven dedicated global or regional clock, or through a clock control block,
provided the clock control block is fed by an output from another PLL or a
pin-driven dedicated global or regional clock. An internally generated global
signal cannot drive the PLL.
Altera Corporation
July 2009
1â85
Stratix II Device Handbook, Volume 2
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