EP2S90F1020C5 Datasheet, PDF (501/768 Pages) Altera Corporation – Stratix II Device Handbook, Volume 1

High-Speed Differential I/O Interfaces with DPA in Stratix II and Stratix II GX Devices
Differential Data Orientation
There is a set relationship between an external clock and the incoming
data. For operation at 1 Gbps and SERDES factor of 10, the external clock
is multiplied by 10, and phase-alignment can be set in the PLL to coincide
with the sampling window of each data bit. The data is sampled on the
falling edge of the multiplied clock. Figure 5–17 shows the data bit
orientation of the 10 mode.
Figure 5–17. Bit Orientation in the Quartus II Software
inclock/outclock
data in
MSB
10 LVDS Bits
LSB
n-1 n-0 9 8 7 6 5 4 3 2 1 0
high-frequency clock
Differential I/O Bit Position
Data synchronization is necessary for successful data transmission at
high frequencies. Figure 5–18 shows the data bit orientation for a channel
operation. These figures are based on the following:
■ SERDES factor equals clock multiplication factor
■ Edge alignment is selected for phase alignment
■ Implemented in hard SERDES
For other serialization factors use the Quartus II software tools and find
the bit position within the word. The bit positions after deserialization are
listed in Table 5–4.
Figure 5–18 also shows a functional waveform. Timing waveforms may
produce different results. Altera recommends performing a timing
simulation to predict actual device behavior.
Altera Corporation
January 2008
5–17
Stratix II Device Handbook, Volume 2