EP2S90F1020C5 Datasheet, PDF (70/768 Pages) Altera Corporation – Stratix II Device Handbook, Volume 1

PLLs & Clock Networks
IOE clocks have row and column block regions that are clocked by eight
I/O clock signals chosen from the 24 quadrant clock resources.
Figures 2–35 and 2–36 show the quadrant relationship to the I/O clock
regions.
Figure 2–35. EP2S15 & EP2S30 Device I/O Clock Groups
IO_CLKA[7:0]
IO_CLKB[7:0]
8
8
I/O Clock Regions
8
IO_CLKH[7:0]
24 Clocks in
the Quadrant
24 Clocks in
the Quadrant
IO_CLKC[7:0]
8
8
IO_CLKG[7:0]
24 Clocks in
the Quadrant
24 Clocks in
the Quadrant
IO_CLKD[7:0]
8
8
8
IO_CLKF[7:0]
IO_CLKE[7:0]
2–52
Stratix II Device Handbook, Volume 1
Altera Corporation
May 2007