EP2S90F1020C5 Datasheet, PDF (285/768 Pages) Altera Corporation – Stratix II Device Handbook, Volume 1

PLLs in Stratix II and Stratix II GX Devices
Figure 1–9. Phase Relationship Between Clock and Data in
Source-Synchronous Mode
Data pin
inclk
Data at register
Clock at register
In source-synchronous mode, enhanced PLLs compensate for clock delay
to the top and bottom IO registers and fast PLLs compensate for clock
delay to the side IO registers. While implementing source-synchronous
receivers in these IO banks, use the corresponding PLL type for best
matching between clock and data delays (from input pins to register
ports).
1 Set the input pin to the register delay chain within the IOE to
zero in the Quartus II software for all data pins clocked by a
source-synchronous mode PLL.
No Compensation Mode
In this mode, the PLL does not compensate for any clock networks. This
provides better jitter performance because the clock feedback into the
PFD does not pass through as much circuitry. Both the PLL internal and
external clock outputs are phase shifted with respect to the PLL clock
input. Figure 1–10 shows an example waveform of the PLL clocks’ phase
relationship in this mode.
Altera Corporation
July 2009
1–21
Stratix II Device Handbook, Volume 2