EP2S90F1020C5 Datasheet, PDF (684/768 Pages) Altera Corporation – Stratix II Device Handbook, Volume 1

Quartus II Software Support
Table 8–9. Stratix II and Stratix II GX Remote System Upgrade Pins
Pin Name
RUnLU
User Mode
Configuration
Scheme
Pin Type
N/A if using
remote system
upgrade in FPP,
PS, AS, or PPA
modes.
I/O if not using
these modes.
Remote
configuration in
FPP, PS, or
PPA
Input
Description
Input that selects between remote update
and local update. A logic high (1.5-V, 1.8-
V, 2.5-V, 3.3-V) selects remote update,
and a logic low selects local update.
When not using remote update or local
update configuration modes, this pin is
available as a general-purpose user I/O
pin.
PGM[2..0]
N/A if using
remote system
upgrade in FPP,
PS, AS, or PPA
modes. I/O if
not using these
modes.
Remote
configuration in
FPP, PS or PPA
Output
When using remote configuration in AS
mode, set the RUnLU pin to high because
AS does not support local update.
These output pins select one of eight
pages in the memory (either flash or
enhanced configuration device) when
using remote update mode.
When not using remote update or local
update configuration modes, these pins
are available as general-purpose user
I/O pins.
Quartus II
Software
Support
Implementation in your design requires an remote system upgrade
interface between the FPGA logic array and remote system upgrade
circuitry. You also need to generate configuration files for production and
remote programming of the system configuration memory. The
Quartus^® II software provides these features.
The two implementation options, altremote_update megafunction
and remote system upgrade atom, are for the interface between the
remote system upgrade circuitry and the FPGA logic array interface.
altremote_update Megafunction
The altremote_update megafunction provides a memory-like
interface to the remote system upgrade circuitry and handles the shift
register read/write protocol in FPGA logic. This implementation is
suitable for designs that implement the factory configuration functions
using a Nios processor in the FPGA.
8–24
Stratix II Device Handbook, Volume 2
Altera Corporation
January 2008