EP2S90F1020C5 Datasheet, PDF (693/768 Pages) Altera Corporation – Stratix II Device Handbook, Volume 1

SII52009-3.3
Introduction
9. IEEE 1149.1 (JTAG)
Boundary-Scan Testing for
Stratix II and Stratix II GX
Devices
As printed circuit boards (PCBs) become more complex, the need for
thorough testing becomes increasingly important. Advances in
surface-mount packaging and PCB manufacturing have resulted in
smaller boards, making traditional test methods (such as; external test
probes and “bed-of-nails” test fixture) harder to implement. As a result,
cost savings from PCB space reductions increases the cost for traditional
testing methods.
In the 1980s, the Joint Test Action Group (JTAG) developed a specification
for boundary-scan testing that was later standardized as the IEEE Std.
1149.1 specification. This Boundary-Scan Test (BST) architecture offers the
capability to test efficiently components on PCBs with tight lead spacing.
This BST architecture tests pin connections without using physical test
probes and captures functional data while a device is operating normally.
Boundary-scan cells in a device can force signals onto pins or capture data
from pin or logic array signals. Forced test data is serially shifted into the
boundary-scan cells. Captured data is serially shifted out and externally
compared to expected results. Figure 9–1 illustrates the concept of BST.
Figure 9–1. IEEE Std. 1149.1 Boundary-Scan Testing
Serial
Data In
Boundary-Scan Cell
IC Pin Signal
Serial
Data Out
Core
Logic
Core
Logic
JTAG Device 1
Tested
Connection
JTAG Device 2
Altera Corporation
9–1
January 2008