EP2S90F1020C5 Datasheet, PDF (463/768 Pages) Altera Corporation – Stratix II Device Handbook, Volume 1

Selectable I/O Standards in Stratix II and Stratix II GX Devices
Table 4–3. I/O Standards Supported for Stratix II and Stratix II GX PLL Pins (Part 2 of 2)
Enhanced PLL (1)
Fast PLL
I/O Standard (2)
Input
Output
Input
1.8-V differential HSTL Class I
1.8-V differential HSTL Class II
1.5-V differential HSTL Class I
1.5-V differential HSTL Class II
LVDS
HyperTransport technology
Differential LVPECL
INCLK
v
v
v
v
v
v
FBIN
EXTCLK
INCLK
v
v
v
v
v
v
v
v
v
v
v
v
v
v
Note to Table 4–3:
(1) The enhanced PLL external clock output bank does not allow a mixture of both single-ended and differential I/O
standards.
(2) Altera does not support 1.2-V HSTL for PLL input pins on column I/O pins.
f
For more information, refer to the PLLs in Stratix II & Stratix II GX
Devices chapter in volume 2 of the Stratix II Device Handbook or the PLLs
in Stratix II & Straix II GX Devices chapter in volume 2 of the Stratix II GX
Device Handbook.
Voltage Levels
Stratix II device specify a range of allowed voltage levels for supported
I/O standards. Table 4–4 shows only typical values for input and output
V_CCIO, V_REF, as well as the board V_TT.
Table 4–4. Stratix II and Stratix II GX I/O Standards and Voltage Levels (Part 1 of 3) Note (1)
Stratix II and Stratix II GX
I/O Standard
LVTTL
LVCMOS
V_CCIO (V)
Input Operation
Output Operation
Top and
Bottom I/O
Banks
Left and
Right I/O
Banks (3)
Top and
Bottom I/O
Banks
Left and
Right I/O
Banks(3)
3.3/2.5
3.3/2.5
3.3
3.3
3.3/2.5
3.3/2.5
3.3
3.3
V_REF (V)
V_TT (V)
Input Termination
NA
NA
NA
NA
Altera Corporation
January 2008
4–25
Stratix II Device Handbook, Volume 2