English
Language : 

EP2S90F1020C5 Datasheet, PDF (615/768 Pages) Altera Corporation – Stratix II Device Handbook, Volume 1
Altera Corporation
January 2008
Configuring Stratix II and Stratix II GX Devices
The Quartus II software only allows the selection of n-bit PS
configuration modes, where n must be 1, 2, 4, or 8. However, you can use
these modes to configure any number of devices from 1 to 8. When
configuring SRAM-based devices using n-bit PS modes, use Table 7–16 to
select the appropriate configuration mode for the fastest configuration
times.
Table 7–16. Recommended Configuration Using n-Bit PS Modes
Number of Devices (1)
1
2
3
4
5
6
7
8
Recommended Configuration Mode
1-bit PS
2-bit PS
4-bit PS
4-bit PS
8-bit PS
8-bit PS
8-bit PS
8-bit PS
Note to Table 7–16:
(1) Assume that each DATA line is only configuring one device, not a daisy chain of
devices.
For example, if you configure three devices, you would use the 4-bit PS
mode. For the DATA0, DATA1, and DATA2 lines, the corresponding SOF
data is transmitted from the configuration device to the device. For
DATA3, you can leave the corresponding Bit3 line blank in the Quartus II
software. On the PCB, leave the DATA3 line from the enhanced
configuration device unconnected.
Alternatively, you can daisy chain two devices to one DATA line while the
other DATA lines drive one device each. For example, you could use the
2-bit PS mode to drive two devices with DATA Bit0 (two EP2S15 devices)
and the third device (EP2S30 device) with DATA Bit1. This 2-bit PS
configuration scheme requires less space in the configuration flash
memory, but can increase the total system configuration time.
A system may have multiple devices that contain the same configuration
data. To support this configuration scheme, all device nCE inputs are tied
to GND, while nCEO pins are left floating. All other configuration pins
(nCONFIG, nSTATUS, DCLK, DATA0, and CONF_DONE) are connected to
every device in the chain. Configuration signals can require buffering to
ensure signal integrity and prevent clock skew problems. Ensure that the
DCLK and DATA lines are buffered for every fourth device. Devices must
be the same density and package. All devices will start and complete
7–63
Stratix II Device Handbook, Volume 2