EP2S90F1020C5 Datasheet, PDF (667/768 Pages) Altera Corporation – Stratix II Device Handbook, Volume 1

Remote System Upgrades with Stratix II and Stratix II GX Devices
Figure 8–3. Page Mode Operation in Stratix II & Stratix II GX FPGAs
Configuration
Memory
SOF 0
Page 0
Configuration
Data
SOF n
Page n
Data[ ]
Stratix II/ Stratix II GX
Device
PGM[ ]
Page Select Pins or
Start Address Register
f
Stratix II and Stratix II GX devices drive out three page address pins,
PGM[2..0], to the MAX II device or microprocessor or enhanced
configuration device. These page pins select between eight configuration
pages. Page zero (PGM[2..0] = 000) must contain the factory
configuration, and the other seven pages are application configurations.
The PGM[] pins are pointers to the start address and length of each page,
and the MAX II device, microprocessor, and enhanced configuration
devices perform this translation.
1 When implementing remote system upgrade with an
intelligent-host-based configuration, your MAX II device or
microprocessor should emulate the page mode feature
supported by the enhanced configuration device, which
translates PGM pointers to a memory address in the
configuration memory. Your MAX II device or microprocessor
must provide a similar translation feature.
For more information about the enhanced configuration device page
mode feature, refer to the Dynamic Configuration (Page Mode)
Implementation section of the Enhanced Configuration Devices (EPC4,
EPC8 & EPC16) Data Sheet chapter in volume 2 of the Configuration
Handbook.
When implementing remote system upgrade with AS configuration, a
dedicated 7-bit page start address register inside Stratix II and
Stratix II GX FPGAs determines the start addresses for configuration
pages within the serial configuration device. The PGM[6..0] registers
form bits [22..16] of the 24-bit start address while the other 17 bits are
Altera Corporation
January 2008
8–7
Stratix II Device Handbook, Volume 2