EP2S90F1020C5 Datasheet, PDF (130/768 Pages) Altera Corporation – Stratix II Device Handbook, Volume 1

Configuration
The PLL_ENA pin and the configuration input pins (Table 3–4) have a
dual buffer design: a 3.3-V/2.5-V input buffer and a 1.8-V/1.5-V input
buffer. The VCCSEL input pin selects which input buffer is used. The 3.3-
V/2.5-V input buffer is powered by V_CCPD, while the 1.8-V/1.5-V input
buffer is powered by V_CCIO. Table 3–4 shows the pins affected by VCCSEL.
Table 3–4. Pins Affected by the Voltage Level at VCCSEL
Pin
VCCSEL = LOW (connected VCCSEL = HIGH (connected
to GND)
to V_CCPD)
nSTATUS (when
used as an input)
nCONFIG
CONF_DONE
(when used as an
input)
DATA[7..0]
nCE
DCLK (when used
as an input)
CS
nWS
3.3/2.5-V input buffer is
selected. Input buffer is
powered by V_{C C P D} .
1.8/1.5-V input buffer is
selected. Input buffer is
powered by V_{C C I O} of the I/O
bank.
nRS
nCS
CLKUSR
DEV_OE
DEV_CLRn
RUnLU
PLL_ENA
VCCSEL is sampled during power-up. Therefore, the VCCSEL setting
cannot change on the fly or during a reconfiguration. The VCCSEL input
buffer is powered by V_CCINT and must be hardwired to V_CCPD or ground.
A logic high VCCSEL connection selects the 1.8-V/1.5-V input buffer, and
a logic low selects the 3.3-V/2.5-V input buffer. VCCSEL should be set to
comply with the logic levels driven out of the configuration device or
MAX^® II/microprocessor.
If you need to support configuration input voltages of 3.3 V/2.5 V, you
should set the VCCSEL to a logic low; you can set the V_CCIO of the I/O
bank that contains the configuration inputs to any supported voltage. If
3–6
Stratix II Device Handbook, Volume 1
Altera Corporation
May 2007