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EP2S90F1020C5 Datasheet, PDF (467/768 Pages) Altera Corporation – Stratix II Device Handbook, Volume 1 | |||
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Altera Corporation
January 2008
Selectable I/O Standards in Stratix II and Stratix II GX Devices
Table 4â5 shows the list of output standards that support on-chip series
termination without calibration.
Table 4â5. Selectable I/O Drivers with On-Chip Series Termination without
Calibration
I/O Standard
3.3-V LVTTL
3.3-V LVCMOS
2.5-V LVTTL
2.5-V LVCMOS
1.8-V LVTTL
1.8-V LVCMOS
1.5-V LVTTL
1.5-V LVCMOS
SSTL-2 Class I
SSTL-2 Class II
SSTL-18 Class I
SSTL-18 Class II
1.8-V HSTL Class I
1.8-V HSTL Class II
1.5-V HSTL Class I
1.2-V HSTL (1)
On-chip Series Termination Setting
Row I/O
50
25
50
25
50
25
50
25
50
50
50
50
50
25
50
50
50
Column I/O
Unit
50
ï
25
ï
50
ï
25
ï
50
ï
25
ï
50
ï
25
ï
50
ï
25
ï
50
ï
25
ï
50
ï
50
ï
50
ï
25
ï
50
ï
25
ï
50
ï
25
ï
50
ï
50
ï
Note to Table 4â5:
(1) 1.2-V HSTL is only supported in I/O banks 4,7, and 8.
To use on-chip termination for the SSTL Class I standard, users should
select the 50-ï on-chip series termination setting for replacing the
external 25-ï RS (to match the 50-ï transmission line). For the
SSTL Class II standard, users should select the 25-ï on-chip series
termination setting (to match the 50-ï transmission line and the near end
50-ï pull-up to VTT).
4â29
Stratix II Device Handbook, Volume 2
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