EP2S90F1020C5 Datasheet, PDF (713/768 Pages) Altera Corporation – Stratix II Device Handbook, Volume 1

IEEE 1149.1 (JTAG) Boundary-Scan Testing for Stratix II and Stratix II GX Devices
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● Check the connections to the V_CC, GND, JTAG, and dedicated
configuration pins on the device.
■ Perform a SAMPLE/PRELOAD test cycle prior to the first EXTEST test
cycle to ensure that known data is present at the device pins when
you enter the EXTEST mode. If the OEJ update register contains a 0,
the data in the OUTJ update register is driven out. The state must be
known and correct to avoid contention with other devices in the
system.
■ Do not perform EXTEST testing during ICR. This instruction is
supported before or after ICR, but not during ICR. Use the
CONFIG_IO instruction to interrupt configuration and then perform
testing, or wait for configuration to complete.
■ If performing testing before configuration, hold nCONFIG pin low.
■ After configuration, any pins in a differential pin pair cannot be
tested. Therefore, performing BST after configuration requires
editing of BSC group definitions that correspond to these differential
pin pairs. The BSC group should be redefined as an internal cell.
1 Refer to the Boundary-Scan Description Language (BSDL)
file for more information on editing.
For more information on boundary scan testing, contact Altera
Applications Group.
Boundary-Scan
Description
Language
(BSDL) Support
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The Boundary-Scan Description Language (BSDL), a subset of VHDL,
provides a syntax that allows you to describe the features of an IEEE Std.
1149.1 BST-capable device that can be tested. Test software development
systems then use the BSDL files for test generation, analysis, and failure
diagnostics.
For more information, or to receive BSDL files for IEEE Std.
1149.1-compliant Stratix II and Stratix II GX devices, visit the Altera web
site at www.altera.com.
Conclusion
The IEEE Std. 1149.1 BST circuitry available in Stratix II and Stratix II GX
devices provides a cost-effective and efficient way to test systems that
contain devices with tight lead spacing. Circuit boards with Altera and
other IEEE Std. 1149.1-compliant devices can use the EXTEST,
SAMPLE/PRELOAD, and BYPASS modes to create serial patterns that
internally test the pin connections between devices and check device
operation.
Altera Corporation
January 2008
9–21
Stratix II Device Handbook, Volume 2