|
EP2S90F1020C5 Datasheet, PDF (172/768 Pages) Altera Corporation – Stratix II Device Handbook, Volume 1 | |||
|
◁ |
Timing Model
Figure 5â6. Measurement Setup for tzx
tZX, Tristate to Driving High
Disable Enable
OE
OE
½ VCCINT
Dout
Din
Din
1 MΩ
Dout
tzh
tZX, Tristate to Driving Low
Disable Enable
OE
½ VCCINT
1 MΩ
OE
Dout Din
Din
Dout
tzl
â1â
½ VCCIO
â0â
½ VCCIO
Table 5â35 specifies the input timing measurement setup.
Table 5â35. Timing Measurement Methodology for Input Pins (Part 1 of 2) Notes (1)â(4)
I/O Standard
LVTTL (5)
LVCMOS (5)
2.5 V (5)
1.8 V (5)
1.5 V (5)
PCI (6)
PCI-X (6)
SSTL-2 Class I
SSTL-2 Class II
SSTL-18 Class I
SSTL-18 Class II
1.8-V HSTL Class I
Measurement Conditions
Measurement Point
VCCIO (V)
3.135
3.135
2.375
1.710
1.425
2.970
2.970
2.325
2.325
1.660
1.660
1.660
VREF (V)
1.163
1.163
0.830
0.830
0.830
Edge Rate (ns)
3.135
3.135
2.375
1.710
1.425
2.970
2.970
2.325
2.325
1.660
1.660
1.660
VM E A S (V)
1.5675
1.5675
1.1875
0.855
0.7125
1.485
1.485
1.1625
1.1625
0.83
0.83
0.83
5â26
Stratix II Device Handbook, Volume 1
Altera Corporation
April 2011
|
▷ |