EP2S90F1020C5 Datasheet, PDF (494/768 Pages) Altera Corporation – Stratix II Device Handbook, Volume 1

Differential Receiver
Figure 5–8 shows receiver output (RX_OUT) after one bit slip pulse with
the deserialization factor set to 4.
Figure 5–8. Data Realignment Timing
inclk
rx_in
32
10
32
10
32
10
rx_outclock
rx_channel_data_align
rx_out
3210
321x
xx21
0321
The data realignment circuit can have up to 11 bit-times of insertion
before a rollover occurs. The programmable bit rollover point can be from
1 to 11 bit-times independent of the deserialization factor. An optional
status port, rx_cda_max, is available to the FPGA from each channel to
indicate when the preset rollover point is reached.
Figure 5–9 illustrates a preset value of four bit-times before rollover
occurs. The rx_cda_max signal pulses for one rx_outclk cycle to
indicate that the rollover has occurred.
Figure 5–9. Receiver Data Re-alignment Rollover
inclk
rx_channel_data_align
rx_outclk
rx_cda_max
Dynamic Phase Aligner
The DPA block takes in high-speed serial data from the differential input
buffer and selects one of eight phase clocks to sample the data. The DPA
chooses a phase closest to the phase of the serial data. The maximum
phase offset between the data and the phase-aligned clock is 1/8 UI,
which is the maximum quantization error of the DPA. The eight phases
5–10
Stratix II Device Handbook, Volume 2
Altera Corporation
January 2008