EP2S90F1020C5 Datasheet, PDF (566/768 Pages) Altera Corporation – Stratix II Device Handbook, Volume 1

Fast Passive Parallel Configuration
Fast Passive
Parallel
Configuration
The key is to ensure the VCCIO voltage of bank 3 is high enough to trip
the VCCIO3 POR trip point on power-up. Also, to make sure the
configuration device meets the V_IH for the configuration input pins based
on the selected input buffer.
Fast passive parallel (FPP) configuration in Stratix II and Stratix II GX
devices is designed to meet the continuously increasing demand for
faster configuration times. Stratix II and Stratix II GX devices are
designed with the capability of receiving byte-wide configuration data
per clock cycle. Table 7–8 shows the MSEL pin settings when using the
FFP configuration scheme.
Table 7–8. Stratix II and Stratix II GX MSEL Pin Settings for FPP Configuration Schemes Notes (1), (2), and
(3)
Configuration Scheme
FPP when not using remote system upgrade or decompression and/or
design security feature
FPP when using remote system upgrade (4)
FPP with decompression and/or design security feature enabled (5)
FPP when using remote system upgrade and decompression and/or
design security feature (4), (5)
MSEL3 MSEL2 MSEL1 MSEL0
0
0
0
0
0
1
0
0
1
0
1
1
1
1
0
0
Notes to Table 7–8:
(1) You must verify the configuration output pins for your chosen configuraiton modes meet the V_IH of the
configuration device. Refer to Table 7–22 for a consolidated list of configuration output pins.
(2) The V_IH of 3.3-V or 2.5-V configuration devices will not be met when the VCCIO of the output configuration pins
is 1.8-V or 1.5-V. Level shifters will be required to meet the input high level voltage threshold V_IH.
(3) The VCCSEL signal does not control TDO or nCEO. During configuration, these pins drive out voltage levels
corresponding to the VCCIO supply voltage that powers the I/O bank containing the pin. For more information
about multi-volt support, including information about using TDO and nCEO in multi-volt systems, refer to the
Stratix II GX Architecture chapter in volume 1 of the Stratix II GX Device Handbook.
(4) These schemes require that you drive the RUnLU pin to specify either remote update or local update. For more
information about remote system upgrade in Stratix II devices, refer to the Remote System Upgrades With Stratix II
& Stratix II GX Devices chapter in volume 2 of the Stratix II Device Handbook or the Remote System Upgrades With
Stratix II & Stratix II GX Devices chapter in volume 2 of the Stratix II GX Device Handbook.
(5) These modes are only supported when using a MAX II device or a microprocessor with flash memory for
configuration. In these modes, the host system must output a DCLK that is 4× the data rate.
FPP configuration of Stratix II and Stratix II GX devices can be performed
using an intelligent host, such as a MAX II device, a microprocessor, or an
Altera enhanced configuration device.
7–14
Stratix II Device Handbook, Volume 2
Altera Corporation
January 2008