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EP2S90F1020C5 Datasheet, PDF (402/768 Pages) Altera Corporation – Stratix II Device Handbook, Volume 1 | |||
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External Memory Standards
Figure 3â2. Clock Generation for External Memory Interfaces in Stratix II and Stratix II GX Devices
LE
IOE
VCC
GND
VCC
DQ
DQ
CK (1)
DK (2)
VCC
GND
VCC
clk
DQ
DQ
CK# (1)
DK# (2)
Notes to Figure 3â2:
(1) CK and CK# are the clocks to the memory devices.
(2) DK and DK# are for RLDRAM II interfaces. You can generate DK# and DK from separate pins if the difference of
the Quartus II softwareâs reported clock-to-out time for these pins meets the RLDRAM II deviceâs tCKDK
specification.
Read and Write Operations
When reading from the memory, DDR and DDR2 SDRAM devices send
the data edge-aligned with respect to the data strobe. To properly read the
data in, the data strobe needs to be center-aligned with respect to the data
inside the FPGA. Stratix II and Stratix II GX devices feature dedicated
circuitry to shift this data strobe to the middle of the data window.
Figure 3â3 shows an example of how the memory sends out the data and
data strobe for a burst-of-two operation.
3â6
Stratix II Device Handbook, Volume 2
Altera Corporation
January 2008
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