EP2S90F1020C5 Datasheet, PDF (644/768 Pages) Altera Corporation – Stratix II Device Handbook, Volume 1

Device Configuration Pins
Device
Configuration
Pins
The following tables describe the connections and functionality of all the
configuration related pins on the Stratix II and Stratix II GX devices.
Table 7–21 summarizes the Stratix II pin configuration.
Table 7–21. Stratix II Configuration Pin Summary (Part 1 of 2)
Bank
3
3
3
3
3
Description
PGM[2..0]
ASDO
nCSO
CRC_ERROR
DATA0
Input/Output
Output
Output
Output
Output
Input
Dedicated
3 DATA[7..1] Input
3 DATA7
Bidirectional
3 RDYnBSY
Output
3
INIT_DONE
Output
3 nSTATUS
Bidirectional
Yes
3 nCE
Input
Yes
3 DCLK
Input
Yes
Output
3
CONF_DONE
Bidirectional
Yes
8 TDI
Input
Yes
8 TMS
Input
Yes
8 TCK
Input
Yes
8 TRST
Input
Yes
8 nCONFIG
Input
Yes
8 VCCSEL
Input
Yes
8 CS
Input
8 CLKUSR
Input
8 nWS
Input
8 nRS
Input
8 RUnLU
Input
8 nCS
Input
7 PORSEL
Input
Yes
7
nIO_PULLUP Input
Yes
Note (1)
Powered By
(2)
(2)
(2)
(2)
(3)
(3)
(2), (3)
(2)
Pull-up
Pull-up
(3)
(3)
(2)
Pull-up
VCCPD
VCCPD
VCCPD
VCCPD
(3)
VCCINT
(3)
(3)
(3)
(3)
(3)
(3)
VCCINT
VCCINT
Configuration Mode
PS, FPP, PPA, RU, LU
AS
AS
Optional, all modes
All modes except
JTAG
FPP, PPA
PPA
PPA
Optional, all modes
All modes
All modes
PS, FPP
AS
All modes
JTAG
JTAG
JTAG
JTAG
All modes
All modes
PPA
Optional
PPA
PPA
PS, FPP, PPA, RU, LU
PPA
All modes
All modes
7–92
Stratix II Device Handbook, Volume 2
Altera Corporation
January 2008