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EP2S90F1020C5 Datasheet, PDF (169/768 Pages) Altera Corporation – Stratix II Device Handbook, Volume 1 | |||
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DC & Switching Characteristics
4. Record the time to VMEAS.
5. Compare the results of steps 2 and 4. The increase or decrease in
delay should be added to or subtracted from the I/O Standard
Output Adder delays to yield the actual worst-case propagation
delay (clock-to-output) of the PCB trace.
The Quartus II software reports the timing with the conditions shown in
Table 5â34 using the above equation. Figure 5â4 shows the model of the
circuit that is represented by the output timing of the Quartus II software.
Figure 5â4. Output Delay Timing Reporting Setup Modeled by Quartus II
VTT
VCCIO
RT
Output Output
RS
Buffer
VMEAS
CL
Outputp
RD
Outputn
GND
GND
Notes to Figure 5â4:
(1) Output pin timing is reported at the output pin of the FPGA device. Additional
delays for loading and board trace delay need to be accounted for with IBIS model
simulations.
(2) VCCPD is 3.085 V unless otherwise specified.
(3) VCCINT is 1.12 V unless otherwise specified.
Figures 5â5 and 5â6 show the measurement setup for output disable and
output enable timing.
Altera Corporation
April 2011
5â23
Stratix II Device Handbook, Volume 1
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