EP2S90F1020C5 Datasheet, PDF (272/768 Pages) Altera Corporation – Stratix II Device Handbook, Volume 1

Enhanced PLLs
External Clock Outputs
Enhanced PLLs 5, 6, 11, and 12 each support up to six single-ended clock
outputs (or three differential pairs). See Figure 1–4.
Figure 1–4. External Clock Outputs for Enhanced PLLs 5, 6, 11 and 12
C0
C1
Enhanced ^C2
PLL
C3
C4
C5
extclken0
(3)
extclken1
(3)
extclken2
(3)
extclken3
(3)
extclken4
(3)
extclken5
(3)
PLL#_OUT0p
(1)
PLL#_OUT0n
(1)
PLL#_OUT1p
(1)
PLL#_OUT1n
(1)
PLL#_OUT2p
(1), (2)
PLL#_OUT2n
(1), (2)
Notes to Figure 1–4:
(1) These clock output pins can be fed by any one of the C[5..0] counters.
(2) These clock output pins are used as either external clock outputs or for external feedback. If the design uses external
feedback input pins, you will lose one (or two, if f_BIN is differential) dedicated output clock pin.
(3) These external clock enable signals are available only when using the altclkctrl megafunction.
Any of the six output counters C[5..0] can feed the dedicated external
clock outputs, as shown in Figure 1–5. Therefore, one counter or
frequency can drive all output pins available from a given PLL. The
dedicated output clock pins (PLL_OUT) from each enhanced PLL are
powered by a separate power pin (e.g., VCC_PLL5_OUT, VCC_PLL6_OUT,
etc.), reducing the overall output jitter by providing improved isolation
from switching I/O pins.
1–8
Stratix II Device Handbook, Volume 2
Altera Corporation
July 2009