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EP2S90F1020C5 Datasheet, PDF (365/768 Pages) Altera Corporation – Stratix II Device Handbook, Volume 1 | |||
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TriMatrix Embedded Memory Blocks in Stratix II and Stratix II GX Devices
Table 2â5 summarizes the byte selection.
Table 2â5. Byte Enable for Stratix II and Stratix II GX M4K Blocks Note (1)
byteena
[3..0]
[0] = 1
[1] = 1
[2] = 1
[3] = 1
data Ã16
[7..0]
[15..8]
-
-
data Ã18
[8..0]
[17..9]
-
-
data Ã32
data Ã36
[7..0]
[15..8]
[23..16]
[31..24]
[8..0]
[17..9]
[26..18]
[35..27]
Note to Table 2â5:
(1) Any combination of byte enables is possible.
M-RAM Blocks
M-RAM blocks support byte enables for any combination of data widths
of 16, 18, 32, 36, 64, and 72 bits. For memory block configurations with
widths of less than two bytes (Ã16/Ã18), the byte-enable feature is not
supported. In the Ã128 and Ã144 simple dual-port modes, the two sets of
byte enable signals (byteena_a and byteena_b) combine to form the
necessary 16 byte enables. In Ã128 and Ã144 modes, byte enables are only
supported when using single clock mode. However, the Quartus II
software can implement byte enables in other clocking modes for Ã128 or
Ã144 widths but will use twice as many M-RAM resources. If clock
enables are used in Ã128 or Ã144 mode, you must use the same clock
enable setting for both the A and B ports. Table 2â6 summarizes the byte
selection for M-RAM blocks.
Table 2â6. Byte Enable for Stratix II and Stratix II GX M-RAM Blocks Note (1)
byteena
[0] = 1
[1] = 1
[2] = 1
[3] = 1
[4] = 1
[5] = 1
[6] = 1
[7] = 1
data Ã16
[7..0]
[15..8]
-
-
-
-
-
-
data Ã18
[8..0]
[17..9]
-
-
-
-
-
-
data Ã32
[7..0]
[15..8]
[23..16]
[31..24]
-
-
-
-
data Ã36 data Ã64 data Ã72
[8..0] [7..0] [8..0]
[17..9] [15..8] [17..9]
[26..18] [23..16] [26..18]
[35..27] [31..24] [35..27]
-
[39..32] [44..36]
-
[47..40] [53..45]
-
[55..48] [62..54]
-
[63..56] [71..63]
Note to Table 2â6:
(1) Any combination of byte enables is possible.
Altera Corporation
January 2008
2â5
Stratix II Device Handbook, Volume 2
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