EP2S90F1020C5 Datasheet, PDF (115/768 Pages) Altera Corporation – Stratix II Device Handbook, Volume 1

Stratix II Architecture
device, PLL 1 can drive a maximum of 10 transmitter channels in I/O
bank 1 or a maximum of 19 transmitter channels in I/O banks 1 and 2. The
Quartus II software may also merge receiver and transmitter PLLs when
a receiver is driving a transmitter. In this case, one fast PLL can drive both
the maximum numbers of receiver and transmitter channels.
Table 2–21. EP2S15 Device Differential Channels Note (1)
Package
484-pin FineLine BGA
672-pin FineLine BGA
Transmitter/
Receiver
Transmitter
Receiver
Transmitter
Receiver
Total
Channels
38 (2)
(3)
42 (2)
(3)
38 (2)
(3)
42 (2)
(3)
PLL 1
10
19
11
21
10
19
11
21
Center Fast PLLs
PLL 2
PLL 3
9
9
19
19
10
10
21
21
9
9
19
19
10
10
21
21
PLL 4
10
19
11
21
10
19
11
21
Table 2–22. EP2S30 Device Differential Channels Note (1)
Package
484-pin FineLine BGA
672-pin FineLine BGA
Transmitter/
Receiver
Transmitter
Receiver
Transmitter
Receiver
Total
Channels
38 (2)
(3)
42 (2)
(3)
58 (2)
(3)
62 (2)
(3)
PLL 1
10
19
11
21
16
29
17
31
Center Fast PLLs
PLL 2
PLL 3
9
9
19
19
10
10
21
21
13
13
29
29
14
14
31
31
PLL 4
10
19
11
21
16
29
17
31
Altera Corporation
May 2007
2–97
Stratix II Device Handbook, Volume 1