EP2S90F1020C5 Datasheet, PDF (392/768 Pages) Altera Corporation – Stratix II Device Handbook, Volume 1

Designing With TriMatrix Memory
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Refer to AN 207: TriMatrix Memory Selection Using the Quartus II Software
for more information on selecting the appropriate memory block.
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Synchronous and Pseudo-Asynchronous Modes
The TriMatrix memory architecture implements synchronous RAM by
registering the input and output signals to the RAM block. The inputs to
all TriMatrix memory blocks are registered providing synchronous write
cycles, while the output registers can be bypassed. In a synchronous
operation, RAM generates its own self-timed strobe write enable signal
derived from the global or regional clock. In contrast, a circuit using
asynchronous RAM must generate the RAM write enable signal while
ensuring that its data and address signals meet setup and hold time
specifications relative to the write enable signal. During a synchronous
operation, the RAM is used in pipelined mode (inputs and outputs
registered) or flow-through mode (only inputs registered). However, in
an asynchronous memory, neither the input nor the output is registered.
While Stratix II and Stratix II GX devices do not support asynchronous
memory, they do support a pseudo-asynchronous read where the output
data is available during the clock cycle when the read address is driven
into it. Pseudo-asynchronous reading is possible in the simple and true
dual-port modes of the M512 and M4K blocks by clocking the read enable
and read address registers on the negative clock edge and bypassing the
output registers.
Refer to AN 210: Converting Memory from Asynchronous to Synchronous for
Stratix and Stratix GX Designs for more information.
Power-up Conditions and Memory Initialization
Upon power up, TriMatrix memory is in an idle state. The M512 and M4K
block outputs always power-up to zero, regardless of whether the output
registers are used or bypassed. Even if an MIF is used to pre-load the
contents of the RAM block, the outputs will still power-up as cleared. For
example, if address 0 is pre-initialized to FF, the M512 and M4K blocks
power up with the output at 00.
M-RAM blocks do not support MIFs; therefore, they cannot be pre-loaded
with data upon power up. M-RAM blocks asynchronous outputs and
memory controls always power up to an unknown state. If M-RAM block
outputs are registered, the registers power up as cleared. When a read is
performed immediately after power up, the output from the read
operation will be undefined since the M-RAM contents are not initialized.
The read operation will continue to be undefined for a given address until
a write operation is performed for that address.
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Stratix II Device Handbook, Volume 2
Altera Corporation
January 2008