EP2S90F1020C5 Datasheet, PDF (265/768 Pages) Altera Corporation – Stratix II Device Handbook, Volume 1

SII52001-4.6
Introduction
1. PLLs in Stratix II and
Stratix II GX Devices
Stratix^® II and Stratix II GX device phase-locked loops (PLLs) provide
robust clock management and synthesis for device clock management,
external system clock management, and high-speed I/O interfaces.
Stratix II devices have up to 12 PLLs, and Stratix II GX devices have up to
8 PLLs. Stratix II and Stratix II GX PLLs are highly versatile and can be
used as a zero delay buffer, a jitter attenuator, low skew fan out buffer, or
a frequency synthesizer.
Stratix II and Stratix II GX devices feature both enhanced PLLs and fast
PLLs. Stratix II and Stratix II GX devices have up to four enhanced PLLs.
Stratix II devices have up to eight fast PLLs and Stratix II GX devices have
up to four PLLs. Both enhanced and fast PLLs are feature rich, supporting
advanced capabilities such as clock switchover, reconfigurable phase
shift, PLL reconfiguration, and reconfigurable bandwidth. PLLs can be
used for general-purpose clock management, supporting multiplication,
phase shifting, and programmable duty cycle. In addition, enhanced
PLLs support external clock feedback mode, spread-spectrum clocking,
and counter cascading. Fast PLLs offer high speed outputs to manage the
high-speed differential I/O interfaces.
Stratix II and Stratix II GX devices also support a power-down mode
where clock networks that are not being used can easily be turned off,
reducing the overall power consumption of the device. In addition,
Stratix II and Stratix II GX PLLs support dynamic selection of the PLL
input clock from up to five possible sources, giving you the flexibility to
choose from multiple (up to four) clock sources to feed the primary and
secondary clock input ports.
The Altera^® Quartus^® II software enables the PLLs and their features
without requiring any external devices.
Altera Corporation
1–1
July 2009