EP2S90F1020C5 Datasheet, PDF (148/768 Pages) Altera Corporation – Stratix II Device Handbook, Volume 1

Operating Conditions
Table 5–2. Maximum Duty Cycles in Voltage Transitions
Symbol
Parameter
V_I
Maximum duty cycles
in voltage transitions
Condition
V_I = 4.0 V
V_I = 4.1 V
V_I = 4.2 V
V_I = 4.3 V
V_I = 4.4 V
V_I = 4.5 V
Maximum
Duty Cycles
Unit
100
%
90
%
50
%
30
%
17
%
10
%
Recommended Operating Conditions
Table 5–3 contains the Stratix II device family recommended operating
conditions.
Table 5–3. Stratix II Device Recommended Operating Conditions (Part 1 of 2) Note (1)
Symbol
Parameter
Conditions
Minimum Maximum Unit
V_CCINT
V_CCIO
V_CCPD
V_CCA
V_CCD
V_I
V_O
Supply voltage for internal logic 100 μs ≤ risetime ≤ 100 ms (3)
Supply voltage for input and
output buffers, 3.3-V operation
100 μs ≤ risetime ≤ 100 ms (3), (6)
Supply voltage for input and
output buffers, 2.5-V operation
100 μs ≤ risetime ≤ 100 ms (3)
Supply voltage for input and
output buffers, 1.8-V operation
100 μs ≤ risetime ≤ 100 ms (3)
Supply voltage for output buffers, 100 μs ≤ risetime ≤ 100 ms (3)
1.5-V operation
Supply voltage for input and
output buffers, 1.2-V operation
100 μs ≤ risetime ≤ 100 ms (3)
Supply voltage for pre-drivers as 100 μs ≤ risetime ≤ 100 ms (4)
well as configuration and JTAG
I/O buffers.
Analog power supply for PLLs 100 μs ≤ risetime ≤ 100 ms (3)
Digital power supply for PLLs 100 μs ≤ risetime ≤ 100 ms (3)
Input voltage (see Table 5–2)
(2), (5)
Output voltage
1.15
3.135
(3.00)
2.375
1.71
1.425
1.14
3.135
1.15
1.15
–0.5
0
1.25
V
3.465
V
(3.60)
2.625
V
1.89
V
1.575
V
1.26
V
3.465
V
1.25
V
1.25
V
4.0
V
V_CCIO
V
5–2
Stratix II Device Handbook, Volume 1
Altera Corporation
April 2011