EP2S90F1020C5 Datasheet, PDF (404/768 Pages) Altera Corporation – Stratix II Device Handbook, Volume 1

External Memory Standards
Figure 3–4. DQ and DQS Relationship During a DDR and DDR2 SDRAM Write Notes (1), (2)
DQS at
FPGA Pin
DQ at
FPGA Pin
Notes to Figure 3–4:
(1) This example shows a write for a burst length of four. DDR SDRAM also supports burst lengths of two.
(2) The write clock signals never go to hi-Z state on RLDRAM II and QDRII SRAM memory interfaces because they use
free-running clocks. However, the general timing relationship between data and the read clock shown in this figure
still applies.
f
For more information on DDR SDRAM and DDR2 SDRAM
specifications, refer to JEDEC standard publications JESD79C and
JESD79-2, respectively, from www.jedec.org, or see AN 327: Interfacing
DDR SDRAM with Stratix II Devices and AN 327: Interfacing DDR
SDRAM with Stratix II Devices.
RLDRAM II
RLDRAM II provides fast random access as well as high bandwidth and
high density, making this memory technology ideal for high-speed
network and communication data storage applications. The fast random
access speeds in RLDRAM II devices make them a viable alternative to
SRAM devices at a lower cost. Additionally, RLDRAM II devices have
minimal latency to support designs that require fast response times.
Interface Pins
RLDRAM II devices use interface pins such as data, clock, command, and
address pins. There are two types of RLDRAM II memory: common I/O
(CIO) and separate I/O (SIO). The data pins in a RLDRAM II CIO device
are bidirectional while the data pins in a RLDRAM II SIO device are
unidirectional. Instead of bidirectional data strobes, RLDRAM II uses
differential free-running read and write clocks to accompany the data. As
in DDR or DDR2 SDRAM, data is sent and captured at twice the system
clock rate by transferring data on the clock’s positive and negative edge.
The commands and addresses still only use one active (positive) edge of
a clock.
If the data pins are bidirectional, as in RLDRAM II CIO devices, connect
them to Stratix II and Stratix II GX DQ pins. If the data pins are
unidirectional, as in RLDRAM II SIO devices, connect the RLDRAM II
device Q ports to the Stratix II and Stratix II GX device DQ pins and
3–8
Stratix II Device Handbook, Volume 2
Altera Corporation
January 2008