EP2S90F1020C5 Datasheet, PDF (324/768 Pages) Altera Corporation – Stratix II Device Handbook, Volume 1

Board Layout
Figure 1–37. External Clock Output Pin Association with Output Power
VCC_PLL5_OUT
PLL5_OUT0p
PLL5_OUT0n
PLL5_OUT1p
PLL5_OUT1n
PLL5_OUT2p
PLL5_OUT2n
Filter each isolated power pin with a decoupling circuit shown in
Figure 1–38. Decouple the isolated power pins with parallel combination
of 0.1- and 0.001-Fceramic capacitors located as close as possible to the
Stratix II or Stratix II GX device.
1–60
Stratix II Device Handbook, Volume 2
Altera Corporation
July 2009