EP2S90F1020C5 Datasheet, PDF (286/768 Pages) Altera Corporation – Stratix II Device Handbook, Volume 1

Clock Feedback Modes
Figure 1–10. Phase Relationship between PLL Clocks in No Compensation
Mode
Phase Aligned
PLL Reference
Clock at the
Input Pin
PLL Clock at the
Register Clock Port (1), (2)
External PLL Clock Outputs (2)
Notes to Figure 1–10.
(1) Internal clocks fed by the PLL are phase-aligned to each other.
(2) The PLL clock outputs can lead or lag the PLL input clocks.
Normal Mode
An internal clock in normal mode is phase-aligned to the input clock pin.
The external clock output pin will have a phase delay relative to the clock
input pin if connected in this mode. In normal mode, the delay
introduced by the GCLK or RCLK network is fully compensated.
Figure 1–11 shows an example waveform of the PLL clocks’ phase
relationship in this mode.
1–22
Stratix II Device Handbook, Volume 2
Altera Corporation
July 2009