EP2S90F1020C5 Datasheet, PDF(475/768 Page) Altera Corporation – Stratix II Device Handbook, Volume 1

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EP2S90F1020C5 Datasheet, PDF (475/768 Pages) Altera Corporation – Stratix II Device Handbook, Volume 1

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Selectable I/O Standards in Stratix II and Stratix II GX Devices

Output Pins

When a voltage-referenced input or bidirectional pad does not exist in a

bank, the number of output pads that can be used in that bank depends

on the total number of available pads in that same bank. However, when

a voltage-referenced input exists, a design can use up to 20 output pads

per VREF pin in a bank.

Bidirectional Pins

Bidirectional pads must satisfy both input and output guidelines

simultaneously. The general formulas for input and output rules are

shown in Table 4â9.

Table 4â9. Bidirectional Pin Limitation Formulas

Rules

Input

Output

Formulas

<Total number of bidirectional pins> + <Total number of VREF

input pins, if any> ï£ï 40 per VREF pin

<Total number of bidirectional pins> + <Total number of

output pins, if any> â <Total number of pins from smallest

OE group, if more than one OE groups> ï£ï 20 per VREF pin

â If the same output enable (OE) controls all the bidirectional pads

(bidirectional pads in the same OE group are driving in and out at the

same time) and there are no other outputs or voltage-referenced

inputs in the bank, then the voltage-referenced input is never active

at the same time as an output. Therefore, the output limitation rule

does not apply. However, since the bidirectional pads are linked to

the same OE, the bidirectional pads will all act as inputs at the same

time. Therefore, there is a limit of 40 input pads, as follows:

<Total number of bidirectional pins> + <Total number of VREF input pins>

ï£ï 40 per VREF pin

â If any of the bidirectional pads are controlled by different OE and

there are no other outputs or voltage-referenced inputs in the bank,

then one group of bidirectional pads can be used as inputs and

another group is used as outputs. In such cases, the formula for the

output rule is simplified, as follows:

<Total number of bidirectional pins> â <Total number of pins from smallest

OE group> ï£ï 20 per VREF pin

Altera Corporation

January 2008

4â37

Stratix II Device Handbook, Volume 2

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