EP2S90F1020C5 Datasheet, PDF (144/768 Pages) Altera Corporation – Stratix II Device Handbook, Volume 1

Hot Socketing Feature Implementation in Stratix II Devices
Figure 4–1. Hot Socketing Circuit Block Diagram for Stratix II Devices
Output
Power On
Reset
Monitor
Weak
R
Pull-Up
Resistor
PAD
Output Enable
Voltage
Tolerance
Control
Hot Socket
Output
Pre-Driver
Input Buffer
to Logic Array
The POR circuit monitors V_CCINT voltage level and keeps I/O pins tri-
stated until the device is in user mode. The weak pull-up resistor (R) from
the I/O pin to V_CCIO is present to keep the I/O pins from floating. The
3.3-V tolerance control circuit permits the I/O pins to be driven by 3.3 V
before V_CCIO and/or V_CCINT and/or V_CCPD are powered, and it prevents
the I/O pins from driving out when the device is not in user mode. The
hot socket circuit prevents I/O pins from internally powering V_CCIO,
V_CCINT, and V_CCPD when driven by external signals before the device is
powered.
Figure 4–2 shows a transistor level cross section of the Stratix II device
I/O buffers. This design ensures that the output buffers do not drive
when V_CCIO is powered before V_CCINT or if the I/O pad voltage is higher
than V_CCIO. This also applies for sudden voltage spikes during hot
insertion. There is no current path from signal I/O pins to V_CCINT or V_CCIO
or V_CCPD during hot insertion. The V_PAD leakage current charges the 3.3-V
tolerant circuit capacitance.
4–4
Stratix II Device Handbook, Volume 1
Altera Corporation
May 2007