EP2S90F1020C5 Datasheet, PDF (525/768 Pages) Altera Corporation – Stratix II Device Handbook, Volume 1

DSP Blocks in Stratix II and Stratix II GX Devices
Figure 6–4 shows the multiplier block architecture.
Figure 6–4. Multiplier Block Architecture
mult_round (1)
mult_saturate (1)
signa (1)
signb (1)
aclr[3..0]
shiftinb
clock[3..0]
shiftina
ena[3..0]
sourcea
Data A
sourceb
Data B
DQ
ENA
CLRN
DQ
ENA
CLRN
Q1.15
Round/
Saturate
(3)
(2)
DQ
ENA
CLRN
Pipeline
Register
DQ
ENA
CLRN
Output
Register
Data Out
mult_is_saturated
Multiplier Block
DSP Block
shiftoutb shiftouta
Notes to Figure 6–4:
(1) These signals are not registered or registered once to match the data path pipeline.
(2) You can send these signals through either one or two pipeline registers.
(3) The rounding and/or saturation is only supported in 18 × 18-bit signed multiplication for Q1.15 inputs.
Input Registers
Each multiplier operand can feed an input register or directly to the
multiplier. The following DSP block signals control each input register
within the DSP block:
■ clock[3..0]
■ ena[3..0]
■ aclr[3..0]
The input registers feed the multiplier and drive two dedicated shift
output lines, shiftouta and shiftoutb. The dedicated shift outputs
from one multiplier block directly feed input registers of the adjacent
multiplier below it within the same DSP block or the first multiplier in the
next DSP block to form a shift register chain, as shown in Figure 6–5. The
Altera Corporation
January 2008
6–9
Stratix II Device Handbook, Volume 2