EP2S90F1020C5 Datasheet, PDF (564/768 Pages) Altera Corporation – Stratix II Device Handbook, Volume 1

Configuration Features
than 00X0 (MSEL[1] = X, “don't care”), VCCSEL=GND selects the higher
I/O bank 3 POR trip point for 2.5-V/3.3-V signaling and VCCSEL=VCCPD
selects the lower I/O bank 3 POR trip point associated with 1.5-V/1.8-V
signaling.
For all configuration modes with MSEL[3..0] not equal to 00X0
(MSEL[1] = X, “don't care”), if VCCIO of configuration bank 3 is powered
by 1.8-V or 1.5-V and VCCSEL = GND, the voltage supplied to this I/O
bank(s) may never reach the POR trip point, which prevents the device
from beginning configuration.
If the VCCIO of I/O bank 3 is powered by 1.5- or 1.8-V and the
configuration signals used require 3.3- or 2.5-V signaling, you should set
VCCSEL to VCCPD to enable the 1.8-/1.5-V input buffers for configuration.
The 1.8-V/1.5-V input buffers are 3.3-V tolerant.
1
The fast passive parallel (FPP) and passive serial (PS) modes
always enable bank 3 to use the POR trip point to be consistent
with 1.8- and 1.5-V signaling, regardless of the VCCSEL setting.
Table 7–6 shows how you should set VCCSEL depending on the
configuration mode, the voltage level on VCCIO3 pins that power bank 3,
and the supported configuration input voltages.
Table 7–6. Supported V_CCSEL Setting Based on Mode, VCCIO3, and Input
Configuration Voltage
Configuration
Mode
All modes
All modes
All modes
—
V_CCIO (Bank 3)
3.3-V/2.5-V
1.8-V/1.5-V
1.8-V/1.5-V
3.3-V/2.5-V
Supported Configuration
Input Voltages
V_CCSEL
3.3-V/2.5-V
3.3-V/2.5-V
1.8-V/1.5-V
1.8-V/1.5-V
GND
V_CCPD (1)
V_CCPD
Not Supported
Note to Table 7–6:
(1) The VCCSEL pin can also be connected to GND for PS (MSEL[3..0]=0010) and
FPP (MSEL[3..0]=0000) modes.
7–12
Stratix II Device Handbook, Volume 2
Altera Corporation
January 2008