EP2S90F1020C5 Datasheet, PDF (574/768 Pages) Altera Corporation – Stratix II Device Handbook, Volume 1

Fast Passive Parallel Configuration
Figure 7–6. FPP Configuration Timing Waveform
nCONFIG
t_CF2ST1
t_CFG
t_CF2CK
Notes (1), (2)
nSTATUS (3)
CONF_DONE (4)
DCLK
DATA[7..0]
User I/O
INIT_DONE
t_STATUS
t_CF2ST0
t_CLK
t_CF2CD
t_CH t_CL
t_ST2CK
t_DH
Byte 0 Byte 1 Byte 2 Byte 3
t_DSU
High-Z
Byte n
(5)
(5)
User Mode
User Mode
t_CD2UM
Notes to Figure 7–6:
(1) This timing waveform should be used when the decompression and design security feature are not used.
(2) The beginning of this waveform shows the device in user-mode. In user-mode, nCONFIG, nSTATUS, and
CONF_DONE are at logic high levels. When nCONFIG is pulled low, a reconfiguration cycle begins.
(3) Upon power-up, the Stratix II or Stratix II GX device holds nSTATUS low for the time of the POR delay.
(4) Upon power-up, before and during configuration, CONF_DONE is low.
(5) DCLK should not be left floating after configuration. It should be driven high or low, whichever is more convenient.
(6) DATA[7..0] are available as user I/O pins after configuration and the state of these pins depends on the
dual-purpose pin settings.
Table 7–9 defines the timing parameters for Stratix II and Stratix II GX
devices for FPP configuration when the decompression and the design
security features are not enabled.
Table 7–9. FPP Timing Parameters for Stratix II and Stratix II GX Devices (Part 1 of 2)
Symbol
Parameter
Min
t_CF2CD nCONFIG low to CONF_DONE low
t_CF2ST0 nCONFIG low to nSTATUS low
t_CFG
nCONFIG low pulse width
2
t_STATUS nSTATUS low pulse width
10
t_CF2ST1 nCONFIG high to nSTATUS high
t_CF2CK nCONFIG high to first rising edge on DCLK
100
t_ST2CK nSTATUS high to first rising edge of DCLK
2
Max
800
800
100 (3)
100 (3)
Notes (1), (2)
Units
ns
ns
µs
µs
µs
µs
µs
7–22
Stratix II Device Handbook, Volume 2
Altera Corporation
January 2008