EP2S90F1020C5 Datasheet, PDF (554/768 Pages) Altera Corporation – Stratix II Device Handbook, Volume 1

Introduction
The configuration scheme is selected by driving the Stratix II or
Stratix II GX device MSEL pins either high or low as shown in Table 7–1.
The MSEL pins are powered by the V_CCIO power supply of the bank they
reside in. The MSEL[3..0] pins have 9-k internal pull-down resistors
that are always active. During power-on reset (POR) and during
reconfiguration, the MSEL pins have to be at LVTTL V_IL and V_IH levels to
be considered a logic low and logic high.
1 To avoid any problems with detecting an incorrect configuration
scheme, hard-wire the MSEL[] pins to V_CCPD and GND, without
any pull-up or pull-down resistors. Do not drive the MSEL[]
pins by a microprocessor or another device.
Table 7–1. Stratix II and Stratix II GX Configuration Schemes (Part 1 of 2)
Configuration Scheme
Fast passive parallel (FPP)
Passive parallel asynchronous (PPA)
Passive serial (PS)
Remote system upgrade FPP (1)
Remote system upgrade PPA (1)
Remote system upgrade PS (1)
Fast AS (40 MHz) (2)
Remote system upgrade fast AS (40 MHz) (2)
FPP with decompression and/or design security
feature enabled (3)
Remote system upgrade FPP with decompression
and/or design security feature enabled (1), (3)
AS (20 MHz) (2)
Remote system upgrade AS (20 MHz) (2)
JTAG-based configuration (5)
MSEL3
0
0
0
0
0
0
1
1
1
1
1
1
(4)
MSEL2
0
0
0
1
1
1
0
0
0
1
1
1
(4)
MSEL1
0
0
1
0
0
1
0
0
1
0
0
1
(4)
MSEL0
0
1
0
0
1
0
0
1
1
0
1
0
(4)
7–2
Stratix II Device Handbook, Volume 2
Altera Corporation
January 2008