EP2S90F1020C5 Datasheet, PDF (430/768 Pages) Altera Corporation – Stratix II Device Handbook, Volume 1

Stratix II and Stratix II GX DDR Memory Support Overview
Figure 3–15. DQ Configuration in Stratix II or Stratix II GX IOE
DFF
(2)
OE
DQ
Note (1)
datain_l
Logic Array
datain_h
OE Register A_OE
DFF
DQ
Output Register A_O
DFF
DQ
TRI
0
1
DQ Pin
outclock (3)
dataout_h
Output Register B_O
DFF
QD
dataout_l
LatcThCLHA
QD
ENA
Input Register A_I
DFF
neg_reg_out
QD
(4)
inclock (from DQS bus)
(5)
Latch C _I
Input Register B_I (6)
Notes to Figure 3–15:
(1) You can use the altdq megafunction to generate the DQ signals. You should, however, use Altera’s memory
controller IP Tool Bench to generate the data path for your memory interface. The signal names used here match
with Quartus II software naming convention.
(2) The OE signal is active low, but the Quartus II software implements this as active high and automatically adds an
inverter before the OE register A_OE during compilation.
(3) The outclock signal for DDR, DDR2 SDRAM, and QDRII SRAM interfaces has a 90° phase-shift relationship with
the system clock. For 300-MHz RLDRAM II interfaces with EP2S60F1020C3, Altera recommends a 75° phase-shift
relationship.
(4) The shifted DQS or DQSn signal can clock this register. Only use the DQSn signal for QDRII SRAM interfaces.
(5) The shifted DQS signal must be inverted before going to the DQ IOE. The inversion is automatic if you use the
altdq megafunction to generate the DQ signals. Connect this port to the combout port in the altdqs
megafunction.
(6) On the top and bottom I/O banks, the clock to this register can be an inverted register A’s clock or a separate clock
(inverted or non-inverted). On the side I/O banks, you can only use the inverted register A’s clock for this port.
3–34
Stratix II Device Handbook, Volume 2
Altera Corporation
January 2008