EP2S90F1020C5 Datasheet, PDF (390/768 Pages) Altera Corporation – Stratix II Device Handbook, Volume 1

Clock Modes
Figure 2–18. Stratix II andStratix II GX Single-Clock Mode in Simple Dual-Port Mode
6 LAB Row
Clocks
6
data[ ]
rdaddress[ ]
DQ
ENA
DQ
ENA
Memory Block
256 ´ 16
Data In _{512 ´ 8}
1,024 ´ 4
2,048 ´ 2
4,096 ´ 1
Read Address
byteena[ ]
DQ
ENA
Data Out
Byte Enable
DQ
ENA
Note (1)
To MultiTrack
Interconnect (3)
wraddress[ ]
rd_addressstall
wr_addressstall
rden (2)
wren
DQ
ENA
DQ
ENA
Write Address
Read Address
Clock Enable
Write Address
Clock Enable
Read Enable
Write Enable
enable
clock
DQ
ENA
Write
Pulse
Generator
Notes to Figure 2–18:
(1) Violating the setup or hold time on the memory block address registers could corrupt the memory contents. This
applies to both read and write operations.
(2) The read enable rden signal is not available in the M-RAM block. An M-RAM block in simple dual-port mode is
always reading the data stored at the current read address location.
(3) Refer to the Stratix II Device Family Data Sheet (volume 1) of the Stratix II Device Handbook or the Stratix II GX Device
Family Data Sheet (volume 1) of the Stratix II GX Device Handbook for more information on the MultiTrack
interconnect.
2–30
Stratix II Device Handbook, Volume 2
Altera Corporation
January 2008