EP2S90F1020C5 Datasheet, PDF (453/768 Pages) Altera Corporation – Stratix II Device Handbook, Volume 1

Selectable I/O Standards in Stratix II and Stratix II GX Devices
Figure 4–14. 1.8-V Differential HSTL Class I Termination
VTT = 0.9 V
VTT = 0.9 V
Differential
Transmitter
50 Ω
50 Ω
Differential
Receiver
Z0 = 50 Ω
Z0 = 50 Ω
Figure 4–15. 1.8-V Differential HSTL Class II Termination
VTT = 0.9 V VTT = 0.9 V
VTT = 0.9 V
VTT = 0.9 V
Differential
Transmitter
50 Ω
50 Ω
50 Ω
50 Ω
Differential
Receiver
Z0 = 50 Ω
Z0 = 50 Ω
Altera Corporation
January 2008
1.5-V Differential HSTL Class I and 1.5-V Differential HSTL Class II
The 1.5-V differential HSTL standard is formulated under EIA/JEDEC
Standard, EIA/JESD8-6: A 1.5-V Output Buffer Supply Voltage Based
Interface Standard for Digital Integrated Circuits.
The 1.5-V differential HSTL specification is the same as the 1.5-V
single-ended HSTL specification. It is used for applications designed to
operate in the 0.0- to 1.5-V HSTL logic switching range, such as QDR
memory clock interfaces. Stratix II and Stratix II GX devices support both
input and output levels operation. Figures 4–16 and 4–17 show details on
the 1.5-V differential HSTL termination.
Stratix II and Stratix II GX devices support 1.5-V differential HSTL I/O
standards in pseudo-differential mode, which is implemented by using
two 1.5-V HSTL single-ended buffers.
4–15
Stratix II Device Handbook, Volume 2