EP2S90F1020C5 Datasheet, PDF (694/768 Pages) Altera Corporation – Stratix II Device Handbook, Volume 1

IEEE Std. 1149.1 BST Architecture
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This chapter discusses how to use the IEEE Std. 1149.1 BST circuitry in
Stratix^® II and Stratix GX devices, including:
■ IEEE Std. 1149.1 BST architecture
■ IEEE Std. 1149.1 boundary-scan register
■ IEEE Std. 1149.1 BST operation control
■ I/O Voltage Support in JTAG Chain
■ IEEE Std. 1149.1 BST circuitry utilization
■ IEEE Std. 1149.1 BST circuitry disabling
■ IEEE Std. 1149.1 BST guidelines
■ Boundary-Scan Description Language (BSDL) support
In addition to BST, you can use the IEEE Std. 1149.1 controller for Stratix II
and Stratix II GX device in-circuit reconfiguration (ICR). However, this
chapter only discusses the BST feature of the IEEE Std. 1149.1 circuitry.
For information on configuring Stratix II devices via the IEEE Std. 1149.1
circuitry, refer to the Configuring Stratix II & Stratix II GX Devices chapter
in volume 2 of the Stratix II Device Handbook, or the Configuring Stratix II
& Stratix II GX Devices chapter in volume 2 of the Stratix II GX Device
Handbook.
1 When configuring via IJAG make sure that Stratix II,
Stratix II GX, Stratix, Cyclone^™ II, and Cyclone devices are
within the first 17 devices in a JTAG chain. All of these devices
have the same JTAG controller. If any of the Stratix II,
Stratix II GX, Stratix, Cyclone II, and Cyclone devices are in the
18th or further position, configuration fails. This does not affect
SignalTap^® II or boundary-scan testing.
IEEE Std. 1149.1
BST Architecture
A Stratix II and Stratix II GX device operating in IEEE Std. 1149.1 BST
mode uses four required pins, TDI, TDO, TMS and TCK, and one optional
pin, TRST. The TCK pin has an internal weak pull-down resistor, while the
TDI, TMS and TRST pins have weak internal pull-ups. The TDO output pin
is powered by V_CCIO in I/O bank 4. All of the JTAG input pins are
powered by the 3.3-V V_CCPD supply. All user I/O pins are tri-stated
during JTAG configuration.
1
For recommendations on how to connect a JTAG chain with
multiple voltages across the devices in the chain, refer to “I/O
Voltage Support in JTAG Chain” on page 9–17.
9–2
Stratix II Device Handbook, Volume 2
Altera Corporation
January 2008