EP2S90F1020C5 Datasheet, PDF (695/768 Pages) Altera Corporation – Stratix II Device Handbook, Volume 1

IEEE 1149.1 (JTAG) Boundary-Scan Testing for Stratix II and Stratix II GX Devices
Table 9–1 summarizes the functions of each of these pins.
Table 9–1. IEEE Std. 1149.1 Pin Descriptions
Pin
TDI
TDO
TMS
TCK
TRST
Description
Test data input
Test data output
Test mode select
Test clock input
Test reset input
(optional)
Function
Serial input pin for instructions as well as test and programming data.
Data is shifted in on the rising edge of TCK.
Serial data output pin for instructions as well as test and programming
data. Data is shifted out on the falling edge of TCK. The pin is tri-stated
if data is not being shifted out of the device.
Input pin that provides the control signal to determine the transitions of
the Test Access Port (TAP) controller state machine. Transitions within
the state machine occur at the rising edge of TCK. Therefore, TMS
must be set up before the rising edge of TCK. TMS is evaluated on the
rising edge of TCK.
The clock input to the BST circuitry. Some operations occur at the
rising edge, while others occur at the falling edge.
Active-low input to asynchronously reset the boundary-scan circuit.
This pin should be driven low when not in boundary-scan operation
and for non-JTAG users the pin should be permanently tied to GND.
The IEEE Std. 1149.1 BST circuitry requires the following registers:
■ The instruction register determines the action to be performed and
the data register to be accessed.
■ The bypass register is a 1-bit-long data register that provides a
minimum-length serial path between TDI and TDO.
■ The boundary-scan register is a shift register composed of all the
boundary-scan cells of the device.
Altera Corporation
January 2008
9–3
Stratix II Device Handbook, Volume 2