EP2S90F1020C5 Datasheet, PDF (60/768 Pages) Altera Corporation – Stratix II Device Handbook, Volume 1

Digital Signal Processing Block
Table 2–5 shows the number of DSP blocks in each Stratix II device.
Table 2–5. DSP Blocks in Stratix II Devices Note (1)
Device DSP Blocks
EP2S15
12
EP2S30
16
EP2S60
36
EP2S90
48
EP2S130
63
EP2S180
96
Total 9 × 9
Multipliers
96
128
288
384
504
768
Total 18 × 18
Multipliers
48
64
144
192
252
384
Total 36 × 36
Multipliers
12
16
36
48
63
96
Note to Table 2–5:
(1) Each device has either the numbers of 9 × 9-, 18 × 18-, or 36 × 36-bit multipliers
shown. The total number of multipliers for each device is not the sum of all the
multipliers.
DSP block multipliers can optionally feed an adder/subtractor or
accumulator in the block depending on the configuration. This makes
routing to ALMs easier, saves ALM routing resources, and increases
performance, because all connections and blocks are in the DSP block.
Additionally, the DSP block input registers can efficiently implement shift
registers for FIR filter applications, and DSP blocks support Q1.15 format
rounding and saturation.
Figure 2–28 shows the top-level diagram of the DSP block configured for
18 × 18-bit multiplier mode.
2–42
Stratix II Device Handbook, Volume 1
Altera Corporation
May 2007