EP2S90F1020C5 Datasheet, PDF (391/768 Pages) Altera Corporation – Stratix II Device Handbook, Volume 1

TriMatrix Embedded Memory Blocks in Stratix II and Stratix II GX Devices
Figure 2–19. Stratix II and Stratix II GX Single-Clock Mode in Single-Port Mode Note (1)
6 LAB Row
Clocks
6
data[ ]
DQ
ENA
Memory Block
256 ´ 16
Data In _{512 ´ 8}
1,024 ´ 4
2,048 ´ 2
4,096 ´ 1
address[ ]
byteena[ ]
DQ
ENA
DQ
ENA
Address
Data Out
Byte Enable
DQ
ENA
To MultiTrack
Interconnect (2)
addressstall
Address
Clock Enable
wren
Write Enable
enable
clock
DQ
ENA
Write
Pulse
Generator
Notes to Figure 2–19:
(1) Violating the setup or hold time on the memory block address registers could corrupt the memory contents. This
applies to both read and write operations.
(2) Refer to the Stratix II Device Family Data Sheet (volume 1) of the Stratix II Device Handbook or the Stratix II GX Device
Family Data Sheet (volume 1) of the Stratix II GX Device Handbook for more information on the MultiTrack
interconnect.
Designing With
TriMatrix
Memory
When instantiating TriMatrix memory, it is important to understand the
features that set it apart from other memory architectures. The following
sections describe the unique attributes and functionality of TriMatrix
memory.
Selecting TriMatrix Memory Blocks
The Quartus II software automatically partitions user-defined memory
into embedded memory blocks using the most efficient size
combinations. The memory can also be manually assigned to a specific
block size or a mixture of block sizes. Table 2–1 on page 2–2 is a guide for
selecting a TriMatrix memory block size based on supported features.
Altera Corporation
January 2008
2–31
Stratix II Device Handbook, Volume 2