EP2S90F1020C5 Datasheet, PDF (490/768 Pages) Altera Corporation – Stratix II Device Handbook, Volume 1

Differential Transmitter
Differential
Transmitter
The Stratix II and Stratix II GX transmitter has dedicated circuitry to
provide support for LVDS and HyperTransport signaling. The dedicated
circuitry consists of a differential buffer, a serializer, and a shared fast
PLL. The differential buffer can drive out LVDS or HyperTransport signal
levels that are statically set in the Quartus^® II software. The serializer
takes data from a parallel bus up to 10 bits wide from the internal logic,
clocks it into the load registers, and serializes it using the shift registers
before sending the data to the differential buffer. The most significant bit
(MSB) is transmitted first. The load and shift registers are clocked by the
diffioclk (a fast PLL clock running at the serial rate) and controlled by
the load enable signal generated from the fast PLL. The serialization
factor can be statically set to 4, 6, 7, 8, or 10 using the
Quartus II software. The load enable signal is automatically generated by
the fast PLL and is derived from the serialization factor setting. Figure 5–3
is a block diagram of the Stratix II transmitter.
Figure 5–3. Transmitter Block Diagram
10
Internal
Logic
Serializer
TX_OUT
diffioclk
Fast PLL _{load_en}
Each Stratix II and Stratix II GX transmitter data channel can be
configured to operate as a transmitter clock output. This flexibility allows
the designer to place the output clock near the data outputs to simplify
board layout and reduce clock-to-data skew. Different applications often
require specific clock to data alignments or specific data rate to clock rate
factors. The transmitter can output a clock signal at the same rate as the
data with a maximum frequency of 717 MHz. The output clock can also
be divided by a factor of 2, 4, 8, or 10, depending on the serialization
factor. The phase of the clock in relation to the data can be set at 0° or 180°
(edge or center aligned). The fast PLL provides additional support for
5–6
Stratix II Device Handbook, Volume 2
Altera Corporation
January 2008